Energy-Efficient Chip-to-Chip Communication at the Extremes of Computing
The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether in the context of high-performance computing, mobile devices or biomedical implants, chip-to-chip communication can take up a significant portion of the overall system power budget. A single interconnect methodology cannot address such a broad range of requirements efficiently.