Institute Seminar: Norman Jouppi
Director, Exascale Computing Lab at HP Labs
System Implications of Integrated Photonics
January 11, 2010 | 2:00PM | ESB 1001
Micron-scale photonic devices integrated with standard CMOS processes have the potential to dramatically increase system bandwidths, performance, and configuration flexibility while reducing system power. Small devices have many advantages: reduced power, increased density, and increased speed. By integrating many thousands of these devices on a chip, photonics could potentially be used for most high-speed off-chip and global on-chip communication. Integrated photonics has many advantages at the board and rack scale as well. Recent high-speed board-level electrical signaling (>2.5GHz) precludes the use of multi-drop busses or communication over long distances on ordinary inexpensive PC board materials. By using photonics, high fan-out and high-fan-in bus structures can be built. Due to the low loss of optical signals versus distance, these structures can even be distributed over rack-scale distances. This dramatically increases system flexibility while reducing interconnect power.
As an example of the potential impact of photonics, I describe a system architecture for the 2017 time frame we call Corona. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-corecommunication and off-stack communication to memory or I/O devices. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We believe that in comparison with an electrically-connected many-core alternative, Corona could provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously significantly reducing power.
Norman P. Jouppi is a Fellow and Director of the Exascale Computing Lab at HP Labs. He is known for his innovation
s in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area, and power. He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio, and physical telepresence. His recent work includes implications of emerging nanophotonic technology on computer systems.
Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, and a master of science in electrical engineering from Northwestern University in 1980. While at Stanford, he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification. Jouppi joined HP in 2002 from Compaq Computer Corp., where he was a Staff Fellow at Compaq’s Western Research Laboratory in Palo Alto, Calif. From 1984 through 1996 he was a consulting assistant/associate professor in the department of electrical engineering at Stanford University. He currently serves as past chair of ACM Special Interest Group on Computer Architecture (SIGARCH), is on the ACM Council and on the Computing Research Association (CRA) board. He is on the editorial board of Communications of the ACM and IEEE Computer Architecture Letters, and is a Fellow of the ACM and the IEEE. He holds more than 35 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.
This event is co-presented with the Computer Engineering Program at UC Santa Barbara.
For more information, visit iee.ucsb.edu or contact Whitney Wegener at whitney [at] iee [dot] ucsb [dot] edu.